In recent years, digitization of the receiving device of analog television broadcasting is progressing from progress of semiconductor technology, and it is important in particular to realize a receiving device that is common through broadcasting systems (NTSC, PAL, SECAM). In this situation, a chroma killer circuit is an important circuit in order to detect the phase state of the burst signal in the television video image signal and specify the signal state which is now under reception as well as the broadcasting system.
Hereinafter, the construction and the operation of the entire video image reproduction device and the prior art chroma killer detection circuit will be described with reference to the drawings.
FIG. 9 is a construction diagram illustrating the entirety of the video image reproduction device. A video image reproduction device 4001 includes a video image signal input terminal 4002, an AD converter 4003, a YC separation circuit 4004, a reference clock generator circuit 4005, a chroma killer detection circuit 4006, a color signal demodulation circuit 4007, a chroma killer control circuit 4008, a luminous signal output terminal 4009, a R-Y signal output terminal 4010, and a B-Y signal output terminal 4011.
The video image signal 4102 which is inputted to the video image signal input terminal 4002 is inputted to the AD converter 4003. The AD converter 4003 is operated with a reference clock 4101 which is outputted from the reference clock generator circuit 4005 to convert the video image input signal 4102 to a digital signal. The digitally converted signal is inputted to the YC separation circuit 4004. The YC separation circuit 4004 is operated with the reference clock 4101 to output a luminous signal component 4103 and a color signal component 4104 which are included in the video image signal 4102. The luminous signal 4103 is outputted to outside the block via the luminous signal output terminal 4009.
The reference clock generator circuit 4005 generates a reference clock, i.e., a burst clock which is synchronized with the burst signal portion of the video image signal 4102. Herein, it is supposed that the clock frequency of the reference clock 4101 is supposed as four times of the burst signal.
Hereinafter, the construction and operation of the reference clock generator circuit 4005 will be described in detail.
The reference clock generator circuit 4005 includes a burst detection circuit 4021, the phase comparator 4022, an accumulation adder 4023, a lamp wave generator circuit 4024, a sinusoidal wave generator circuit 4025, a DA converter 4026, an LPF 4027, a four times frequency multiplier circuit 4028, and a four times frequency divider circuit 4029.
The color signal component 4104 is inputted to the phase comparator 4022 and the burst detection circuit 4021. The burst detection circuit 4021 detects the burst signal included in the color signal component 4104, and outputs a burst gate pulse 4120 which is being ON during the burst signal period, thereby indicating the presence of the burst signal. The burst gate signal 4120 is inputted to the phase comparison circuit 4022, the chroma killer detection circuit 4006, and the color signal demodulation circuit 4007. The four times frequency division circuit 4029 carries out a four times frequency division of the reference clock 4101 which is synchronized with the frequency of four times as the frequency of the burst signal, and inputs the signal having the frequency that is equal to that of the burst signal into the phase comparator 4022. The phase comparator 4022 carries out a phase comparison on the color signal component 4104 and the signal which is generated by the four times frequency division circuit 4029. The phase comparison is carried out during the period during which the burst gate pulse 4120 is ON, i.e., during the period during when the burst signal is present, and the result is inputted to the accumulation adder 4023 as a phase error information for a burst lock. The accumulation adder 4023 carries out accumulation addition for the phase error information, and the result is inputted to the lamp wave generator circuit 4024. The lamp wave generator circuit 4024 generates a lamp wave having an inclination of the lamp wave that is equal to the output of the accumulation adder 4023. The SIN wave generator circuit 4025 builds in therein a SIN wave ROM having N pieces of addresses, and when it is assumed that the output of the lamp wave generator circuit 4024 is “X” and the SIN wave output is “Y”, Y=sin(X/N) is satisfied.
Herein, the accumulation adder 4023 has an offset for its center value, and when it is in a burst lock, the phase error information is zero, and therefore, the accumulation addition result does not reflect it and the center value is outputted. In other words, the center value is selected so that the SIN wave which is synchronized with the burst value is generated from the SIN wave generator circuit 4025. While the burst signal frequency is assigned to any of the 4.43 MHz, or 3.58 MHz dependent on the broadcasting system, it takes any of appropriate center values dependent on the received broadcasting. On the other hand, when the phase error is not zero, in order to acquire burst lock, the accumulation adder 4023 varies its center value, and controls the inclination of the lamp wave. Thereby, it is possible to always acquire the burst lock.
Then, the output of the SIN wave generator circuit 4025 is converter into an analog signal by the DA converter 4026, discrete noise components therein are removed by the LPF 4027, and the result signal is outputted with taking clocks which are obtained by the four times multiplier circuit 4028 being synchronized with the four times frequency of the burst signal as reference clock signals 4101 to external circuits.
The color signal components 4104, the reference clock 4101, and the bust gate pulse 4120 are inputted to the color signal reproduction circuit 4007. The color signal demodulation circuit 4007 is operated with the period of the reference clock 14101, and carries out phase demodulation with employing the phases of the burst signal portions which are detected with the burst gate pulse 4120 as references and the results are inputted to the chroma killer control circuit as R-Y signal and B-Y signal, respectively.
The chroma killer detection circuit 4006 detects the abnormality state of the burst signal (i.e., carries out chroma killer detection) on the basis of the color signal components 4104, the reference clocks 4101, and the burst gate pulse 4120, and outputs the result as the chroma killer signal 4140.
The chroma killer control circuit 4008 has a construction so as to halt the output of the demodulation output from the color signal demodulation circuit 4007 when it detects the chroma killer from the chroma killer detection circuit 4006, and the results are outputted from the R-Y signal output terminal 4010 as the R-Y signal 4150 and from the B-Y signal output terminal 4011 as the B-Y signal 4051, respectively.
Next, the construction and operation of the chroma killer detection circuit 4006 will be described with reference to FIG. 5.
The chroma detection circuit 4006 includes a first flip flop 5001, a second flip flop 5002, a third flip flop 5003, a burst cos θ data selection circuit 5004, a threshold setting circuit 5005, a comparator 5006, an up down counter 5007, an OR circuit 5008, a counter upper limit detection circuit 5009, and a counter lower limit detection circuit 5010.
The color signal components 4104 are inputted to the first flip flop 5001 ad the burst cos θdata selection circuit 5004. The output of the first flip flop 5001 is inputted to the second flip flop 5003 and the burst cos θdata selection circuit 5004. The output of the second flip flop 5002 is inputted to the third flip flop 5003 and the burst cos θ data selection circuit 5004. The first flip flop 5001, the second flip flop 5002, and the third flip flop 5003 are operated with reference clocks 4101, respectively.
Here, the color signal components 4104 will be described in detail. In the NTSC, PAL systems, the color signal components 4104 include color signals which are phase modulated, and they are represented by formulae with supposing the carries are sinusoidal waves, as follows:R sin(ωT+θ)
Here, R denotes amplitude, ω denotes an angular velocity, and fsc denotes a carrier frequency which is about 3.58 MHz in the case of NTSC system. θ denotes a color component information that is phase modulated, and in the burst signal portion thereof serving as a reference for the color component information, it is phase modulated such that θ is 180° in the case of NTSC system. T denotes a sampling period and the chroma killer detection circuit 4006 is operated with the reference clock 4101, i.e., clocks which are synchronized with the four times frequency of the burst signal. Accordingly, when it is supposed as t=(¼fsc), the T takes values such as {0, 1t, 2t, 3t, . . . }. With it is supposed that the above-described signal components are inputted, the input of the first flip flop 5001 becomes as follows, when T=0 is assumed,input of first flip flop 5001 is R sin(θ) (when T=0)  (1),and similarly,input of second flip flop 5002 is R cos(θ) (when T=t)  (2),input of third flip flop 5003 is −R sin(θ) (when T=2t)  (3),output of third flip flop 5003 is −R cos(θ) (when T=3t)  (4),and
the respective carrier frequency components of the respective formulae (1) to (4) are removed, thereby remaining only θ components. Herein, the examples of the above-described formulae (1) to (4) are not limited thereto, but the result of the order of R sin(θ), R cos (θ), −R sin(θ), −R cos(θ) is surely obtained.
For example, since θ in the burst signal portion is 180°, the followings are obtained in the example of the above (1) to (4):R sin(180)=0  (1)′R cos(180)=−R  (2)′−R sin(180)=0  (3)′−R cos(180)=R  (4)′
When the information θ is replaced into vector diagrams which are based on the R-Y components and the B-Y components as shown in FIG. 6, the burst signals in the NTSC system become as 601. Herein, the color signal components 4104 are rotated with the period of the burst signal on the circle of radius R, and if they are burst locked, it is meant that the data sampling is carried out at the timings of 602, 603, 604, and 605 as shown in FIG. 6. Further, in the examples of above (1) to (4), the sampled data at the timing of 602 is R sin(θ) which is an input to the first flip flop 5001, the sampled data at the timing of 603 is R cos(θ) which is an input to the second flip flop 5002, the sampled data at the timing of 604 is −R sin(θ) which is an input to the third flip flop 5003, and the sampled data at the timing of 605 is −R cos(θ) which is an output from the third flip flop 5003.
The burst cos θ data selection circuit 5004 outputs the burst signal information which is required for the detection of the chroma killer signal. The burst signal has only the value of B-Y signal components as represented by the vector 601, and becomes as (2)′. Therefore, the data of (2)′ which is sampled at the timing of 603 among the above (1)′ to (4)′ is selected, and it is used for the chroma killer detection which is performed then.
Now, since in the usual signal state both of amplitude and phase are stable, the data “−R” is continued to be sampled at the timing of 603. On the other hand, when the input is carried put in abnormality states such as weak electric field environment, VTR input, or a different broadcasting system input, it is not possible to sample the input data “−R”. The comparator 5006 selects whether the sampled data is in the normal state or in the abnormal state, and its result is inputted to the up down counter 5007.
FIG. 7 illustrates a method of selecting sampled data. Numeral 701 denotes the output of the threshold setting circuit which takes an arbitrary value on the B-Y components. The comparator 5006, which takes the value 701 as the threshold value of the B-Y components, judges it is in the normal state when there is a vector in the region 702 in the vector diagram and makes an UP signal inputted to the up down counter 5007, while judges it is in the abnormal state when there is a vector in the region of 703 and makes a DOWN signal inputted to the up down counter 5007. The up down counter 5007 counts the comparison result of the comparator 5006 and makes the counted result to the counter upper limit detection circuit 5009 and the counter lower limit detection circuit 5010. The counter upper limit detection circuit 5009 makes, when the counted result of the up down counter 5007 has reached the upper limit value, a signal indicating that fact inputted to the OR circuit 5008. The counter lower limit detection circuit 5010 makes, when the counted result of the up down counter 5007 has reached the lower limit value, a signal indicating that fact inputted to the OR circuit 5008, and further, outputs this signal as a chroma killer signal 4140 to the outside. The OR circuit 5008 carries out such a control that the up down counter 5007 is held.
The conditions on which the up down counter 5007 is held are satisfied during when the counter upper limit detection circuit 5009 has detected the upper limit value, when the counter lower limit detection circuit 5010 has detected the lower limit value, or when the input signal is not in the burst portion. Until when the counter lower limit detection circuit 5010 detects the lower limit value while the comparison result of the comparator 5006 being counted by the up down counter 5007, the DOWN signal is inputted as abnormal state to the up down counter 5007, and when the abnormality state of the burst signal is continued to be detected, the chroma killer detection is turned ON.
Patent document 1: Japanese Published Patent Application No. 2001-265591